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triple channel synchronous step - down switcher with integrated fet advanced datasheet IDTP9120 march 12, 2014 1 ? 2014 integrated device technology, inc . features ? input voltage range: 2.7 v to 5 . 5 v ? three step - down converters with integrated fets ? buck1: 2 a ? b uck2: 2 a ? buck3: 3a ? buck 3 to operate in buck or switch mode ? factory programmable output voltage: 0.8 - 3.4v ? automatic pfm/pwm or forced pwm mode ? switching frequency 2 m h z ? optional programmable sequence mode ? power good and/or power on reset output ? - 40 c to +85 c operating temperature range ? package: qfn 24 - ld 4 x 4 mm x 0. 8 mm (nbg24) application s point of load regulation in a variety of low power applications: ? solid state disk drive (ssd) power management ? low power usb powered applications ? set top box / tv power supply ? portable gaming description IDTP9120 is a fully integrated power management ic designed to provide three programmable voltage rails from a single 5v or 3.3v input rail with high efficiency and low quiescent currents in sleep mode or no - load condition. the device offers selectable dir ect buck enable inputs or programmable sequencing with power good and power on reset generation. to support low power operation, the IDTP9120 supports both sleep and standby mode s . the IDTP9120 is available in a 4 mm x 4 mm, 24 - ld, q fn package and is guaranteed to operate over the ambient temperature range - 40c to +85c . simplified application diagram p v i n 2 p g n d 3 l x 3 f b 3 p v i n 1 p g n d 2 f b 2 l x 2 p v i n 3 v r e f ( o p t i o n a l ) v i n s e l d e v s l p i n g p i o 1 5 g p o 1 6 g p i o 1 7 v i n v g n d p g n d 1 f b 1 l x 1 v o u t 1 v o u t 2 v o u t 3 i n p u t v o l t a g e g p i o 1 4 p v i n 2 p g n d 3 l x 3 f b 3 p v i n 1 p g n d 2 f b 2 l x 2 p v i n 3 v r e f ( o p t i o n a l ) v i n s e l g p i o 1 5 g p o 1 6 g p i o 1 7 v i n p g n d 1 f b 1 l x 1 v o u t 1 v o u t 2 v o u t 3 i n p u t v o l t a g e g p i o 1 4 v g n d i d t p 9 1 2 0 w i t h v i n s e l ( p i n 4 ) i n s w i t c h c o n f i g u r a t i o n f o r v o u t 3 i d t p 9 1 2 0 w i t h v i n s e l ( p i n 4 ) i n b u c k c o n f i g u r a t i o n f o r v o u t 3 g p i 3 d e v s l p i n g p i 3
IDTP9120 advanced datasheet march 12, 2014 2 ? 2014 integrated device technology, inc. ordering guide table 1 C ordering summary part number marking package 1 ambient temp. range shipping carrier quantity p 9120 - 00 n b gi p 9120 - 00 n b gi qfn - 24 4x 4 x0. 75mm 2 4 - ld - 40c to +85c tray 490 p 9120 - xx n b gi p 9120 - xx n b gi qfn - 24 4x 4 x0. 75mm 2 4 - ld - 40c to +85c tray 490 p 9120 - xx n b gi 8 p 9120 - xx n b gi qfn - 24 4x 4 x0. 75mm 2 4 - ld - 40c to +85c tape and reel 2,500 additional ordering information: the IDTP9120 will be sampled in - 00 configuration, with all user configurable otp registers at default state (0). once a final customer configuration has been defined, a con figuration specific - xx id will be assigned and used for order and marking. absolute maximum rat ings stresses above the ratings listed below can cause p ermanent damage to the IDTP9120 . these ratings are stre ss ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specificati ons is not implied. exposure to absolute maximum rating conditions for extended periods can affect pr oduct reliability. electrical parameters are guaranteed only over the recommended operating temperature range. table 2 C absolute maximum ratings symbol parameter min max unit pvin1, pvin2, pvin 3 to pgnd regulator input voltage - 0.3 6.0 v v in to gnd s upply for device - 0.3 6.0 v lx1, lx2, lx3 regulator switch nodes - 0.3 6.0 v fb1, fb2, fb3 regulator feedback pins - 0.3 3.6 v all other pins - 0.3 6.0 v t j operating junction temperature 1 25 c t s storage temperature 150 c t solder soldering temperature (10 seconds) 260 c 1 see package information (page 24 ) for additional details. i d t p 9 1 2 0 C x x n b g i 8 t & r o p t i o n : 8 = t & r , b l a n k = n o t e m p e r a t u r e g r a d e : i = - 4 0 c t o + 8 5 c p a c k a g e c o d e d e v i c e i d p m i c c o d e p o w e r p r e f i x c o n f i g u r a t i o n i d
IDTP9120 advanced datasheet march 12, 2014 3 ? 2014 integrated device technology, inc. table 3 - package thermal resistivity symbol description conditions value units ? ja thermal resistance ( qfn - 24 ) junction to ambient 4 0 ? c/w jb thermal characterization parameter ( qfn - 24 ) junction to board 23 ? c/w p d maximum package power dissipation 2.5 w esd rating (hbm) human body model (all pins except 20, 21) ? 2000v (hbm) human body model (only pins 20, 21) ? 5 00 v (cdm) charged device model (all pins) ? 5 00 v per jedec spec, the qfn - 24 package is rated at msl3. this thermal rating was calculated based on a jedec standard 4 - layer board with dimensions 3in x 4.5in in still air conditions. actual thermal resistance will be affected by pcb size, solder joint qualit y, pcb layer count, copper thickness, air flow, altitude, and other unlisted variables. for the qfn - 24 package, the 2.8mm x 2.8mm ep is connected to ground plane with a matrix of 3x3 pcb thermal vias plated through from top t o bottom layers. actual thermal resistance will be affected by pcb size, solder joint quality, pcb layer count, copper thickness, air flow, altitude, and oth er unlisted variables. electrical character istics table 4 C general electrical characteristics typical va lues at 25 c, unless noted. v pvin 1 = v pvin 2 = v pvin 3 = vin= 5v . c o( buck1 ) = c o( buck2 ) = 10 f , c o( buck3 ) = 20 f, l 1 =l2= l3 = 1.0 h .
IDTP9120 advanced datasheet march 12, 2014 4 ? 2014 integrated device technology, inc. symbol parameter conditions min typ max unit v vin input voltage range 2.7 5.5 v uvlo threshold, vin rising v insel > 1v, buck3 in switch (3.3v) mode 2.95 3 3.05 v uvlo threshold, vin falling 2.65 2.7 2.75 v uvlo threshold, vin rising vinsel=0v, buck3 in buck (5v) mode 4.35 4.4 4.45 v uvlo threshold, vin falling 3.95 4.0 4.05 v i q(vin) vin quiescent current device in sleep mode ( vref disable, devslpin floating ) . <1 a device in active mode, all bucks = off 10 8 a v il low level input voltage all inputs 0.65 0.85 v v ih high level input voltage all inputs 1.25 1.45 v i pd pull down current gpio14,15,17 , and gpi3 1 a i pu pull up current devslpin @ vin=5v 5 8 1 0 a r pu pull up resistor selectable for gp i o14,15,17 , gpo16 and gpi3 50 k t sd thermal shutdown 135 c v pg pg detection threshold % of selected output voltage in buck mode, % of v pvin3 in switch mode 10 % i od max drive output in push - pull configuration, v ol =0.4v , v fbx 1.8v 4 ma in open drain configuration, v ol =0.4v 12 ma v ref reference voltage output voltage v fb (buck1) /2 v c vref output capacitor v ref 0.1 f i vref reference voltage output current 1. 0 ma
IDTP9120 advanced datasheet march 12, 2014 5 ? 2014 integrated device technology, inc. electrical character istics table 5 C buck1 electrical characteristics v o( buck1 ) = 1.8 v. typical values at 25c, unless noted. v pvin 1 = v pvin 2 = v pvin 3 = vin= 5v . c o( buck1 ) = c o( buck2 ) = 10 f , c o( buck3 ) = 20 f, l 1=l2=l3 =1.0 h . symbol parameter conditions min typ max unit v pvin 1 input voltage range 2.7 5.5 v v o( buck1 ) output voltage range 0. 8 3. 4 v regulation voltage accuracy - 2 2 % line regulation v pvin 1 = 3 .0 v to 5v 0.01 0.04 %/v load regulation i out 1 = 0.2a to 2 a, pwm mode 0.5 mv/a offset voltage in pfm mode v o(pfm) = v o(pwm) + v offset pfm mode 15 mv i q( buck1 ) quiescent current adder enabled, no load, pfm mode 2 5 a i op(buck1 ) continuous operating dc current t j < 115c 1.8 a i lim(buck1 ) peak inductor current 2 2.5 a r (on) high side switch 110 153 m low side switch 56 78 m r dis( buck1 ) output discharge resistance 500 65 0 9 00 f sw( buck1 ) switching frequency pwm mode 1.89 2 2.1 mhz t ssr(buck1 ) soft - start ramp rate 4 8 12 mv/s i fb 1 fb1 input bias current 6 8 a c o( buck1 ) output capacitor 10 f l o(buck1 ) output inductor 1 h
IDTP9120 advanced datasheet march 12, 2014 6 ? 2014 integrated device technology, inc. electrical characteristics table 6 C buck2 electrical characteristics v o( buck2 ) = 1.2 v . typical values at 25c, unless noted. v pvin 1 = v pvin 2 = v pvin 3 = vin= 5v . c o( buck1 ) = c o( buck2 ) = 10 f , c o( buck3 ) = 20 f, l 1=l2=l3 = 1.0 h . symbol parameter conditions min typ max unit v pvin 2 input voltage range 2.7 5.5 v v o( buck2 ) output voltage range 0. 8 3. 4 v regulation voltage accuracy - 2 2 % line regulation v pvin 2 = 3 .0 v to 5v 0.01 0.04 %/v load regulation i out 2 = 0.2a to 2 a, pwm mode 0.5 mv/a offset voltage in pfm mode v o(pfm) = v o(pwm) + v offset pfm mode 15 mv i q( buck2 ) quiescent current adder enabled, no load, pfm mode 25 a i op(buck2 ) continuous operating dc current t j < 115c 1.8 a i lim(buck2 ) peak inductor current 2 2.5 a r (on) high side switch 110 153 m low side switch 56 78 m r dis( buck2 ) output discharge resistance 500 650 9 00 f sw( buck2 ) switching frequency pwm mode 1.89 2 2.1 mhz t ssr(buck2 ) soft - start ramp rate 4 8 12 mv/s i fb 2 fb2 input bias current 6 8 a c o( buck2 ) output capacitor 10 f l o(buck2 ) output inductor 1 h
IDTP9120 advanced datasheet march 12, 2014 7 ? 2014 integrated device technology, inc. electrical characteristics table 7 C buck3 C electrical characteristics v o( buck3 ) = 3.3 v typical values at 25c, unless noted. v pvin 1 = v pvin 2 = v pvin 3 = vin= 5v . c o( buck1 ) = c o( buck2 ) = 10 f , c o( buck3 ) = 20 f, l 1=l2=l3 =1.0 h . symbol parameter conditions min typ max unit in buck mode (vinsel=low) v pvin 3 input voltage range 2.7 5.5 v v o(buck3 ) output voltage range 0. 8 3. 4 v regulation voltage accuracy - 2 2 % line regulation v pvin 3 = 3 .6 v to 5v 0.01 0.15 %/v load regulation i out 3 = 0.2a to 2.4 a, pwm mode 0.4 0.5 mv/a offset voltage in pfm mode v o(pfm) = v o(pwm) + v offset pfm mode 15 mv i q(buck3 ) quiescent current adder enabled, no load, pfm mode 28 a i op(buck 3 ) continuous operating dc current t j < 115c 2. 3 a i lim(buck3 ) peak inductor current 2. 6 3 a r (on) high side switch 64 93 m low side switch 45 61 m r dis(buck3 ) output discharge resistance 5 00 650 9 00 f sw(buck3 ) switching frequency pwm mode 1.89 2 2.1 mhz t ssr(buck 3 ) soft - start ramp rate 8 12 mv/s i fb 3 fb3 input bias current 9 11 a c o( buck3 ) output capacitor 20 f l o(buck3 ) output inductor 1 h in switch mode (vinsel=high), c o(buck3 ) = 10 f, v pvin 3 = 3.3 v v pvin 3 input voltage range 2.7 3.6 v i shdn(buck3 ) shutdown current 1 a i q(buck3 ) quiescent current no load 10 a i op(buck3 ) continuous operating dc current t j < 115c 2 . 4 a i lim(buck3 ) current limitation 2.8 3 a r (on) high side switch 64 93 m r dis(buck3 ) output discharge resistance 300 800 t ssr(buck3 ) soft - start ramp rate 16 mv/s c o( buck3 ) output capacitor 2 f
IDTP9120 advanced datasheet march 12, 2014 8 ? 2014 integrated device technology, inc. pin configuration an d description figure 1 , device pinout (top view) , 0.5mm pitch qfn - 24, 4x4x0.75mm table 8 C pin functions by pin number # label type description 1 vgnd gnd device ground connection 2 vref a reference output [ vref= vout (buck 1 ) /2 ] 3 gpi3 di general purpose input (see modes of operation , page 9 ) 4 vinsel di logic input to select function of channel 3 ( logic low = buck operation, h igh = switch operation ) and uvlo thresholds . 5 devslpin di logic input to activate sleep mode (l ogic l ow = normal operation, floating = sleep operation ) . 6 fb1 a feedback connection buck 1 7 lx1 a inductor connection buck 1 8 pgnd1 gnd power ground buck 1 9 pvin1 pwr power supply input buck 1 10 pvin2 pwr power supply input buck 2 11 pgnd2 gnd power ground buck 2 12 lx2 a inductor connection buck 2 13 fb2 a feedback connection buck 2 14 gpio14 d i o general purpose input / output (see modes of operation , page 9 ) 15 gpio15 dio general purpose input / output (see modes of operation , page 9 ) 16 gpo16 do general purpose output (see modes of operation , page 9 ) 17 gpio17 dio general purpose input / output (see modes of operation , page 9 ) 18 fb3 a feedback connection buck 3 (buck mode) or output (switch mode) 19 pgnd3 gnd power ground buck 3 20 lx3 a inductor connection buck 3 (buck mode) or output (switch mode) 21 lx3 a 22 pvin3 pwr power supply input buck 3 23 pvin3 pwr 24 vin pwr device supply input ep ep gnd exposed pad, connect to heat sink ground plane v g n d v r e f g p i 3 v i n s e l d e v s l p i n f b 1 1 2 3 4 5 6 p g n d 1 p v i n 1 p v i n 2 p g n d 2 l x 2 l x 1 7 8 9 1 0 1 1 1 2 f b 2 g p i o 1 4 g p i o 1 5 g p o 1 6 g p i o 1 7 f b 3 1 8 1 7 1 6 1 5 1 4 1 3 p g n d 3 l x 3 l x 3 p v i n 3 p v i n 3 v i n 2 4 2 3 2 2 2 1 2 0 1 9 i d t p 9 1 2 0 e p
IDTP9120 advanced datasheet march 12, 2014 9 ? 2014 integrated device technology, inc. functiona l description: overview the IDTP9120 support several modes to control the 3 b uck regulators and to generate status information like pg (power good) or por (power on reset). various device features can be configured during production using one time programmable fuse memory (otp) . during evaluation, the options can be evaluated using the IDTP9120 evaluation kit ( IDTP9120 - eval). the IDTP9120 otp memory is organized into four fuse banks with 34 bits each. bank0 and 1 are used for idt internal trimming and calibration. bank2 and 3 are used for customer specific device configuration. modes of operation device power states device operates in three basic power states controlled by the devslpin pin and one optional state (standby) when in mode 3 . regulator control options (mode 0..3) the IDTP9120 supports four different control options for the buck regulator. the functionality of gpi3, gpio14,15,17 and gpo16 is different for each of the options. (mode[1:0] = otp bank3[1:0]) figure 2 . device power states table 9 C buck control options mode [1:0] d escription gpi3 gpio14 gpio15 gpo16 gpio17 0 ( default ) buck regulators controlled by individual enable pins (en1, en2, en3) nc en1 en2 porb en3 1 special sequencing option . nc coldboot socready porb devslpr l y 2 buck regulators controlled by master enable pin (men) w/ sequence men porb pg1 pg2 pg3 3 buck regulators controlled by master enable pin (men) w/ sequence and standby mode support men standby pg1 pg2 pg3/porb s l e e p o n d e v s l p i n ( p i n 5 ) = h i g h o r f l o a t i n g d e v s l p i n ( p i n 5 ) = l o w n o p o w e r v i n > v u v l o s t a n d b y m o d e 3 o n l y v i n < v u v l o s t a n d b y ( g p i o 1 4 p i n 1 4 ) = l o w s t a n d b y ( g p i o 1 4 p i n 1 4 ) = h i g h
IDTP9120 advanced datasheet march 12, 2014 10 ? 2014 integrated device technology, inc. mode0 C individual buck control with IDTP9120 configured for mode0, all three regulators are individually controlled via enx input pin. the porb output can be configured to indicat e various power up conditions. mode1 C special sequencing option with IDTP9120 configured for mode1, a specific state machine will control the regulators. the sequence has been implemented for specific control lers used in solid state disk (ssd) applications. the sequencing details are documented in the following state diagrams. for further details on the special sequencing option, please contact idt. device start up: (1) input supply ramps - up. (2) devslpin is pulled low, device starts - up. (3) device started - up, vout 2 starts - up. (4) vout2 ramped - up, vout3 starts - up. (5) vout3 ramped - up, vout 1 starts - up. (6) porb de - asserts high. (7) socready (from controller) asserts high. note: buck voltages and sequence shown is default and can be re - programmed. figure 3 , mode1 - device start up device enters devslp: (1) devslpin asserts high. (2) if socready is high, devslprly is asserted high. otherwise devslpin is ignored, devslprly remains low. (3) device is waiting for socready to de - assert low. socready is expected to go low within 500ms. (4) porb is asserted low. (5) devslprly de - asserts low. (6) vout2 shuts down. (7) vout 2 ramped - down. vout3 shuts down. (8) vout 1 shut s down. figure 4 , mode1 - device enters devslp x x x d e v s l p i n s o c r e a d y p o r b c o l d b o o t d e v s l p r l y v o u t 3 ( 3 . 3 v ) v o u t 1 ( 1 . 8 v ) v o u t 2 ( 1 . 2 v ) v i n ( 5 v / 3 . 3 v ) h i g h - z s t a t u s i g n o r e d 1 3 4 5 6 7 a c t i v e m o d e 2 d e v s l p i n s o c r e a d y p o r b c o l d b o o t d e v s l p r l y v o u t 3 ( 3 . 3 v ) v o u t 1 ( 1 . 8 v ) v o u t 2 ( 1 . 2 v ) v i n ( 5 v / 3 . 3 v ) 1 2 3 4 5 6 7 < 1 0 m s p u l s e s i g n o r e d 8
IDTP9120 advanced datasheet march 12, 2014 11 ? 2014 integrated device technology, inc. device exits devslp : (1) devslpin de - asserts low. (2) coldboot de - asserts high, vout 2 starts - up. (3) vout2 ramped - up, vout3 starts - up. (4) vout3 ramped - up, vout 1 start s - up. (5) vout1 ramped - up, porb de - asserts high. (6) device is waiting for socready to assert high. (7) coldboot asserts low. figure 5 . mode1 - device enters devslp device shut - down : (1) vin falls below the uvlo threshold, porb asserts low. (2) after 2ms delay, vout 1 ramps down. (3) vout3 ramps down. (4) vout 2 and vref ramp down. figure 6 . mode1 - device shut - down mode2 C m aster e nable pin (men) w ith sequence with IDTP9120 configured for mode 2 , a configurable state machine will ramp up/down all 3 regulators controlled by the men pin . the porb output can be configured to indicate various power up conditions. individual power good output pins indicate the regulator output being established. mode3 C m aster e nable pin (men) w ith sequence and standby mode with IDTP9120 configured for mode3, a configurable state machine will ramp up/down all 3 regulators controlled by the men pin. the porb output can be configured to indicate various power up conditions. individual po wer good output pins indicate the regulator output being established. in addition to mode2, mode3 supports the standby mode entered by asserting the standby pin. during standby, buck1,2 and/or 3 will be turned off without sequencing. the configuration is p rogrammable via otp. d e v s l p i n s o c r e a d y p o r b c o l d b o o t d e v s l p r l y v o u t 3 ( 3 . 3 v ) v o u t 1 ( 1 . 8 v ) v o u t 2 ( 1 . 2 v ) v i n ( 5 v / 3 . 3 v ) 1 2 3 4 5 6 7 < 1 0 m s p u l s e s i g n o r e d s t a t u s i g n o r e d s t a t u s i g n o r e d d e v s l p i n s o c r e a d y p o r b c o l d b o o t d e v s l p r l y v o u t 3 ( 3 . 3 v ) v o u t 1 ( 1 . 8 v ) v o u t 2 ( 1 . 2 v ) v i n ( 5 v / 3 . 3 v ) 1 2 3 4 u v l o
IDTP9120 advanced datasheet march 12, 2014 12 ? 2014 integrated device technology, inc. pin description devslpin this pin allows the ic to enter and exit sleep mode. sleep mode is the lowest power state of the device and is activated when devslpin is logic high . the device will be i n normal operation when devslpin is logic low . see figure 2 C device power states. for 1ua sleep mode operation, leave this pin floating. in floating operation, it is internally pulled up to ~ 1.5v. if pulled to vin (between 3.0v and 6.0v), leakage curre nt will flow between ~10ua to ~18ua respectively . vinsel this pin allows the function of buck 3 to be changed to a switch function. logic low on this pin puts the channel into buck configuration, and a logic high on this pin puts the channel into switch c onfiguration. the uvlo threshold is also dependent on the vinsel configuration. see table 4 C general electrical characteristics for details. pvin 1, pvin2, pvin3 pvinx is each buck converters respective power supply input. they provide power to the internal mosfets for the switch mode regulator. their operating rang e is 2.7v to 5.5v, and a 10 f capacitor must be placed as close as possible to each of the respective pins. a second 10 f capacitor should be used with pvin3 because of the greater current sourcing capability of this channel. because the capacitance valu e decrea s es with voltage, a 10 v rated x7r ceramic capacitors must be used. x7r is preferred over x5r because the derating with x7r is less. fo r best performance, each of these power supply inputs is to be connected together on a dedi cated circ uit board power plane, and the trace going from these pins , to the dedicated power plane , must be made as short as possible. y5v capacitors are not recommended because of their general low performance with respect to temperature, voltage derating, and hig her resistance at high frequenc ies, minimizing their ability to filter out high frequency noise. vin vin is the power supply input for the bias and control portion of the integrated circuit. it too has an operating range of 2.7v to 5.5v, and a 2.2 f 10v rated x7r capacitor must be pla ced as close as possible to its pin. vin should also be tied to the same power plane that the pvinx pins are tied to with as short a trace as possible . do not use y5v capacitors. pgnd1, pgnd2, pgnd3 these are the dedi cated ground pins for each of the respective power supplies . the traces from these pins , to a dedicated ground plane must be made as short and wide as possible. vgnd vgnd is the ground pin for the bias and control portion of the integrated circuit. the trace from this pin, to a dedicated ground plane, should be made as short as possible. ep this is the exposed pad on the bottom side of the ic. it must be connected to a top or bottom circuit board ground plane to maximize the thermal di ssipation perf ormance of the ic . vref the vref pin t racks the output voltage of buck 1, at half its value. a 2.2 f 6.3v rated x7r capacitor must be connected a t this pin when enabled . this feature should be disabled in the otp setting and left floating when not needed. fb1, fb2, fb3 fb1, fb2, fb3 are the respective feedback pins of the output voltage for each buck converter. the lsb of the outputs for each channel is 25mv from 0.8000v to 3.3375v. in the l ayout, the feedback traces should be kept as short as possible an d should never run parallel to the inductors nor to the inductor trace leading to the inductor switching pin. feedback trac es should always cross inductor s and inductor traces on separate planes and at right angles. lx1, lx2, lx3 lx1, lx2, lx3 are the switching pins of the respective buck converters. the IDTP9120 is optimized for 1 h s mall footprint chip inductors , and connect to the swit ching pin s . the inductors must be placed as close as possible to the lx pins themselves. gpi3 , gpio14, gpio15, gpo 16, gpio17 these pins have multiple function s , s ee table 9 for device mode depended mode function.
IDTP9120 advanced datasheet march 12, 2014 13 ? 2014 integrated device technology, inc. component selection the IDTP9120 is a high performance triple dc - dc step down convert e r that satisfies the solution si ze demands of miniature portable electronic devices . it has t wo 2a outputs and one 3a output in a 4mm x 4mm qfn package . o nly three external components are required per channel (cin, cout, l) . because it is designed to automatically switch to a pulse fr equency modulation scheme at light loads, the IDTP9120 is able to maintain high efficiency across the entire load range while providing ultra - fast load transient response. input capacitor a 10 f ceramic capacitor or greater must be placed close to each pvin pin for e ach channel for bypassing. for the vin pin, a 2.2 f 10v capacitor is s uf ficient because the vin pin is powering the low power internal circuitry of the ic. output capacitor a 10 f or greater ceramic capacitor must be placed close to each output inductor. increasing the output capacitance will lower output ripple and improve load transient response but could also increase solution size or cost. the voltage rating of the output capacitor must be at least 6.3v . inductor selection the IDTP9120 has been designed for use with a 1.0 h inductor. a larger value inductor will produce lower output voltage ripple, but a slightly smaller inductor value will produce faster transient response. the best compromise is a 1.0 h inductor. the inductor must be rated for the maximum peak current. selection of the inductor needs to ensure maximum operating current not just the dc current , and can be rated for a 40c temperature rise . this maximum operating current or p eak current for a buck converter can be calculated using equation 1 eq (1); where r is the inductor current ripple ratio and equal to eq (2). eq (2); where l and f are the indu ctor and switching frequency. simplifying gives equation 3: eq (3). equation 3 shows that the peak inductor current is inversely related to the switching frequency and inductance . in other words, the lower the switching frequency or inductance, the higher the peak current. peak current also increases as input voltage increases. the value of the inductor depends on the application . a validated inductor is the toko 1239as - h - 1r 0 m .
IDTP9120 advanced datasheet march 12, 2014 14 ? 2014 integrated device technology, inc. typical operating characteristics typical values at 25c, unless noted. v pvin 1 = v pvin 2 = v pvin 3 = vin= 5v . c o( buck1 ) = c o( buck2 ) = 10 f , c o( buck3 ) = 20 f, l 1=l2=l3 = 1.0 h . figure 7 . channel 1 efficiency figure 8 . channel 2 efficiency figure 9 . channel 3 efficiency figure 10 . channel 3 line regulation 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency (%) load current (a) efficiency vs load current vin=5v, vo1=1.8v auto pfm/pwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency (%) load current (a) efficiency vs load current vin=5v, vo2=1.2v auto pfm/pwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency (%) load current (a) efficiency vs load current vin=5v, vo3=3.3v auto pfm/pwm - 1.0% - 0.5% 0.0% 0.5% 1.0% 4.5 5 5.5 line regulation (%) vin (v) line regulation vo3=3.3v 0.8a 1.0a 1.2a 1.4a 1.6a 1.8a
IDTP9120 advanced datasheet march 12, 2014 15 ? 2014 integrated device technology, inc. figure 11 . channel 1 line regulation figure 12 . channel 2 line regulation figure 13 . channel 1 load regulation figure 14 . channel 2 load regulation - 0.100% - 0.050% 0.000% 0.050% 0.100% 4.5 5 5.5 line regulation (%) vin (v) line regulation vo1=1.8v 0.8a 1.0a 1.2a 1.4a 1.6a 1.8a - 0.100% - 0.050% 0.000% 0.050% 0.100% 4.5 5 5.5 line regulation (%) vin (v) line regulation vo2=1.2v 0.8a 1.0a 1.2a 1.4a 1.6a 1.8a - 0.10% - 0.05% 0.00% 0.05% 0.10% 0 1 2 3 output voltage accuracy (%) load current (a) load regulation vin=5v, vo1=1.8v ch1 vout=1.8v - 0.10% - 0.05% 0.00% 0.05% 0.10% 0 1 2 3 output voltage accuracy (%) load current (a) load regulation vin=5v, vo2=1.2v ch2 vo=1.2v
IDTP9120 advanced datasheet march 12, 2014 16 ? 2014 integrated device technology, inc. figure 15 . channel 3 load regulation figure 16 . channel 1 l oad transient response figure 17 . all channel startup waveforms figure 18 . channel 1 switch node switching frequency - 0.10% - 0.05% 0.00% 0.05% 0.10% 0 1 2 3 output voltage accuracy (%) load current (a) load regulation vin=5v, vo3=3.3v ch3 vo=3.3v
IDTP9120 advanced datasheet march 12, 2014 17 ? 2014 integrated device technology, inc. figure 19 . sleep quiescent current figure 20 . quiescent current over temperature 0 1 2 3 4 5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 quiescent current (ua) vin (v) sleep mode quiescent current devslpin pin floating, vref=disable 0 20 40 60 80 100 120 - 40 - 20 0 20 40 60 80 quiescent current (ua) temperature ( c) quiescent current over temperature vref disable, devslpin floating, no load, pfm mode, vin=5v quiescent current over temperature
IDTP9120 advanced datasheet march 12, 2014 18 ? 2014 integrated device technology, inc. otp register map ping the following table lists all configurable otp registers available in the IDTP9120 . the registers can be programmed for evaluation purpose using the IDTP9120 evaluation kit ( IDTP9120 - eval) with the included gui software. the final production configuration will be programmed by idt during final test. ( bank t 0 ) trim bits (default) parametric trim descriptions t0 [ 29 ] (0) devslp mode support: sets device behavior when supply is initially applied. 0 : device always powers up independent of devslpin pin state. ssd (solid state disk) application mode. 1 : device powers up only when devslpin is low. ( bank t 1 ) trim bits (default) parametric trim descriptions t1 [ 22:21 ] (00) buck1 slope compensation select: device option for buck 1. to be selected based on inductor value and expected pwm duty cycle. 0 0 : slope comp=nominal 01 : slope comp=+20% 10 : slope comp=+100% 11 : slope comp=+40% t1 [ 24:23 ] (00) buck2 slope compensation select: device option for buck 2. to be selected based on inductor value and expected pwm duty cycle. 00 : slope comp=nominal 01 : slope comp=+20% 10 : slope comp=+100% 11 : slope comp=+40% t1 [ 26:25 ] (00) buck3 slope compensation select: device option for buck 3. to be selected based on inductor value and expected pwm duty cycle. 00 : slope comp=nominal 01 : slope comp=+20% 10 : slope comp=+100% 11 : slope comp=+40%
IDTP9120 advanced datasheet march 12, 2014 19 ? 2014 integrated device technology, inc. ( bank t2) trim bits (default) parametric trim descriptions t2 [ 0 ] (0) buck1 transconductance selection : relevant for all modes 0 : nominal 1 : 3x transconductance t2 [ 1 ] (0) buck1 bandwidth selection : relevant for all modes 0 : nominal 1 : 2x bandwidth t2 [ 2 ] (0) buck1 forced pwm mode : relevant for all modes 0 : auto - switching between pwm & pfm modes 1 : forced pwm mode t2 [ 3 ] (0) buck2 transconductance selection : 0 : nominal 1 : 3x transconductance t2 [ 4 ] (0) buck2 bandwidth selection : 0 : nominal 1 : 2x bandwidth t2 [ 5 ] (0) buck2 forced pwm mode : 0 : auto - switching between pwm & pfm modes 1 : forced pwm mode t2 [ 6 ] (0) buck3 transconductance selection : 0 : nominal 1 : 3x transconductance t2 [ 7 ] (0) buck3 bandwidth selection : 0 : nominal 1 : 2x bandwidth t2 [ 8 ] (0) buck3 forced pwm mode : 0 : auto - switching between pwm & pfm modes 1 : forced pwm mode t2 [ 10:9 ] (00) power - o ff sequencer delay 1: relevant only when mode[1:0]?00 relevant only when mode[1:0]?00
IDTP9120 advanced datasheet march 12, 2014 20 ? 2014 integrated device technology, inc. ( bank t2) trim bits (default) parametric trim descriptions t2 [ 15:13 ] (000) buck power - off sequence selection : relevant only when mode[1:0]?00 000 : buck2 ? buck3 ? buck1 001 : buck2 ? buck1 ? buck3 010 : buck1 ? buck2 ? buck3 011 : buck1 ? buck3 ? buck2 100 : buck3 ? buck1 ? buck2 101 : buck3 ? buck2 ? buck1 110 : buck1 ? buck2 & buck3 111 : buck2 ? buck1 & buck3 t2[18:16] (000) porb output boolean operator selection: pg=power good 000 : pg1 & pg2 & pg3 001 : pg1 010 : pg2 011 : pg3 100 : pg1 & pg2 101 : pg1 & pg3 110 : pg2 & pg3 111 : reserved t2 [ 19 ] (0 ) gpi3 internal pull - up enable : 0 : disable (1 m a pull - down to vgnd) 1 : enable (100k? pull - up to vin) t2[20] unused t2[21] (0 ) gpio14 internal pull - up enable : 0 : disable (1 m a pull - down to vgnd when pin configured as input) 1 : enable (50k? pull - up to supply voltage selected by gpio14_vio) t2[22] (0 ) gpio14 open - drain output select : relevant only when pin configured as output. 0 : push - pull output 1 : open - drain output t2[23] (0 ) gpio14 i/o voltage select : for both input buffer and push - pull output driver. 0 : vout3 (fb3) 1 : vout1 (fb1) t2[24] (0) gpio15 internal pull - up enable : 0 : disable (1 m a pull - down to vgnd when pin configured as input) 1 : enable (50k? pull - up to supply voltage selected by gpio15_vio) t2[25] (0 ) gpio15 open - drain output select : relevant only when pin configured as output. 0 : push - pull output 1 : open - drain output t2[26] (0 ) gpio15 i/o voltage select : for both input buffer and push - pull output driver. 0 : vout3 (fb3) 1 : vout1 (fb1) t2[27] (0 ) gpo16 internal pull - up enable : 0 : disable 1 : enable (50k? pull - up to supply voltage selected by gpo16_vo)
IDTP9120 advanced datasheet march 12, 2014 21 ? 2014 integrated device technology, inc. t2[28] (0 ) gpo16 open - drain output select : 0 : push - pull output 1 : open - drain output t2[29] (0 ) gpo16 output voltage select : for push - pull output driver. 0 : vout3 (fb3) 1 : vout1 (fb1) t2[30] (0 ) gpio17 internal pull - up enable : 0 : disable (1 m a pull - down to vgnd when pin configured as input) 1 : enable (50k? pull - up to supply voltage selected by gpio17_vio) t2[31] (0 ) gpio17 open - drain output select : relevant only when pin configured as output. 0 : push - pull output 1 : open - drain output t2[32] (0 ) gpio17 i/o voltage select : for both input b uf fer and push - pull output driver. 0 : vout3 (fb3) 1 : vout1 (fb1) t2[33] (0 ) vref output disable: 0 : vref = 0.5 x vout1(fb1) 1 : vref output disabled ( bank t 3 ) trim bits (default) parametric trim descriptions t3 [ 1:0 ] (0 0) device i/o configuration and control : 00 : individual regulator enable via pins 01 : special sequence mode 10 : master enable control with programmable sequencing 11 : master enable control with programmable sequencing + sleep mode support t3 [ 2 ] (0 ) tsd & uvlo fault disable : used for device characterization and burn - in only. 0 : fault event shuts down all buck regulators (programmed sequence) 1 : fault ignored t3 [ 5:3 ] (0 00) buck power - on sequence selection : relevant only when mode[1:0]?00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? relevant only when mode[1:0]=11
IDTP9120 advanced datasheet march 12, 2014 22 ? 2014 integrated device technology, inc. ( bank t 3 ) trim bits (default) parametric trim descriptions t3 [ 7 ] (0 ) buck2 sleep mode support : relevant only when mode[1:0]=11 relevant only when mode[1:0]=11 relevant only when mode[1:0]?00 relevant only when mode[1:0]?00 103d : 3.3375v
IDTP9120 advanced datasheet march 12, 2014 23 ? 2014 integrated device technology, inc. application information figure 21 . minimum component schematic of IDTP9120. bill of materials # description package manufacturer part number ic1 IDTP9120-00nbgi 4x4qfn idt l1-l3 1uh 2520/1008 toko 1239as-h-1r0m c1-c3, c10 10uf, 10v, x7r 0805/2012 c0805c106k8ractu c4-c7 10uf, 6.3v, x7r 1206/3216 c1206c106k9ractu c8-c9 2.2uf, 10v, x7r 0603/1608 06036c225kat2a
www.idt.com 6024 silver creek valley road san jose, california 95138 tel: 800 - 345 - 7015 disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at idts sole di scretion. all information in this document, including descriptions of product features and performance, is subject to change withou t notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in c ustomer products. the information contained herein is prov ided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idts products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual pr operty rights of others. this document is presented only as a guide and does not convey any license under intellectual proper ty rights of idt or any third parties. idts products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an expre ss, written agreement by idt. integrated dev ice technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks u 2014 1 os and designs, are the property of idt or their respective third party owners. ? copyright 2014 . all rights reserved. IDTP9120 advanced datasheet error! unknown document property name. 2 4 ? 2014 integrated device technology, inc. package information please refer to the documents located under http://www.idt.com/package/nbg24 for detailed package outline, recommended footprint, carrier and rohs information. IDTP9120 is using the p1 - nbg24 package option (ep size: 2.8mm)

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